1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device such as an electrically programmable and erasable flash memory.
2. Description of the Related Art
In an electrically programmable and erasable non-volatile semiconductor memory device such as a flash memory, when a data is to be written in a memory cell, it is necessary for potentials to be applied to a control gate and a drain of the memory cell. However, the potentials are unnecessarily applied to memory cells to which the data is not to be written. This problem results from a memory array block structure and affects data holding performance of the memory cell.
FIG. 1 is a circuit diagram illustrating a part of the structure of a conventional flash memory. Referring to FIG. 1, the conventional flash memory is composed of memory cell array blocks 10 and 11. In each of the memory cell array blocks 10 and 11, a plurality of memory cells C000 to C0mn or C100 to C1mn are arranged in a matrix manner. The source terminals of the memory cells for each array block 10 or 11 are connected in common to a common source node such that a plurality of memory cell data stored in the memory cells can be collectively erased. The drain terminals of the plurality of memory cells C000 to C0mn or C100 to C1mn are connected to a plurality of bit lines BL00 to BL0m or BL10 to BL1m for every column, respectively. The set of bit lines BL00 to BL0m for the memory cell array block 10 and the set of bit lines BL10 to BL1m for the memory cell array block 11 are electrically independent from each other. The control gates of the plurality of memory cells C000 to C0mn and C100 to C1mn are connected to a plurality of word lines WL0 to WLn for every row, respectively. The word lines WL0 to WLn are connected in common to the memory cell array blocks 10 and 11.
The conventional flash memory is also composed of source voltage supplying circuits 20 and 21 for supplying predetermined source voltages to the common source terminals of the memory cell array blocks 10 and 11, respectively. The source voltage supplying circuit 20 includes N-type MOS transistors N01 and N02, and a P-type MOS transistor P01. The MOS transistors N01, N02 and P01 receive control signals SB0, SG0 and EB0 supplied from a control circuit (not shown) at the gates, respectively. The source voltage supplying circuit 21 includes N-type MOS transistors N11 and N12, and a P-type MOS transistor P11. The MOS transistors N11, N12 and P11 receive, at the gates, signals SB1, SG1 and EB1 supplied from the control circuit (not shown), respectively.
The conventional flash memory is further composed of a source bias voltage generating circuit 200 including a circuit section 201 for the memory cell array block 10. The source bias voltage generating circuit 200 includes a circuit section having the same circuit structure as the circuit section 201 for the array block 11. FIG. 2 is a circuit diagram illustrating the structure of the circuit section 201. Referring to FIG. 2, the circuit section 201 is composed of a P-type MOS transistor PT0 and N-type MOS transistors NT0 and NT1. These MOS transistors are connected in series in this order between the power supply Vpp and the ground line. The circuit section 201 is also composed of resistors R1 to Rn which are connected in series between the ground line and the power supply Vpp for generating a reference voltage. A signal BSB which is in a low level in a write operation to the memory cell array block 11 is supplied to the gate of the MOS transistor NT1 and supplied to the gate of the MOS transistor PT0 in an inverted form. The gate of the MOS transistor NT0 is connected to a node between the resistors Rk and Rk+1.
Referring to FIG. 1 again, the relation between the respective terminal potentials when a data is written in the memory cell C000 of the memory cell array block 10 as a selected memory cell of a selected block will be described. In this case, the write operation is not performed to the memory cells C000 to C00n, C010 to C0mn and C100 to C1mn, that is, these memory cells are the non-selected memory cells. A write drain voltage of about 6 V is applied onto the memory cells C000 to C00n connected to the bit line BL00, and the bit lines BL01 to BL0m and BL10 to BL1m are in the open state. A write control gate voltage of about 12 V is applied onto the memory cells C000 to C0m0 and C100 to C1m0 connected to the word line WL0 and the word lines WL1 to WLn are set to 0 V. A write source voltage of 0 V is applied from the source voltage supplying circuit 20 to the source terminals of the memory cells C000 to C0mn via the common source node CS0, because the control signal SG0 is in the H level. At this time, hot electrons are generated between the source terminal and the drain terminal of this memory cell C000 and injected into a floating gate (FG) of the selected memory cell, so that the threshold voltage of the selected memory cell C000 rises. In the flash memory, the data is written by making the threshold voltage of the selected memory cell rise in this manner.
In this case, the non-selected memory cells C001 to C00n receive the same write drain voltage as the selected memory cell C000. Also, the memory cells C010 to C0m0 and C100 to C1m0 receive the same write control gate (CG) voltage as the selected memory cell C000. As a result, a problem of data holding performance occurs in these non-selected memory cells. Especially, the memory cells C100 to C1m0 are in the memory cell array block 11 different from the memory cell array block 10 in which the selected memory cell C000 is present. However, the memory cells C100 to C1m0 receive the same write control gate voltage as the selected memory cell C000. When the erase operation and the write operation are repeated many times to the memory cell array block 10, the write control gate voltage is also applied to the control gates of the memory cells in the memory cell array block 11 for a long time period.
The application time period during when the non-selected memory cells of the memory cell array block 11 receive the unnecessary write control gate voltage can be expressed by the following equation. EQU TG={TW.times.NB.times.(NA-1).times.NCYC}{TW.times.(NB1)}
where TG is the application time (a gate disturb time) during when the unnecessary write control gate voltage is applied, TW is a write time period, NB is the number of bit lines/one memory cell array block, NA is the number of array blocks in which the word lines are connected in common, and NCYC is the number of times of write operation. The first term of the above equation is the application time period of the write control gate voltage to the memory cell, e.g., C100 when the write operation is performed to the memory cell array block, e.g., 10 in the above case. The second term of the equation is the application time period of the write control gate voltage to the memory cell C100 when the write operation is performed to the memory cell array block. The number of times of the write operation NCYC has great influence to the application time period TG. Therefore, it could be considered that the application time period TG to a memory cell is greatly influenced by the first term. In the currently available product, 10.sup.5 times are guaranteed.
Next, the problem of data holding performance caused in case of receiving the unnecessary write control gate voltage will be described. FIG. 3A is a diagram illustrating each of the terminal voltages, electric fields, and the directions of movement of electrons in the memory cells C010 to C0m0 and C100 to C1m0 which receive the same write control gate voltage as the written cell C000.
Referring to FIG. 3A, when the high write control gate voltage Vg of about 12 V is applied to the control gate (CG) of the memory cell, when the source terminal (S) is set to the ground potential, and when the drain terminal (D) is set to the voltage of about 6 V, the electric field directs from the control gate CG toward the source, the drain and the channel section (between the source and the drain). Also, because the electric field is strong, electrons pass through an oxide film by tunneling phenomenon and are accumulated in the floating gate (FG). This phenomenon is referred to as gate disturb hereinafter. The longer this gate disturb time period TG becomes, the more the threshold voltage of the non-selected memory cell rises. At last, a data holding error will occur. The memory cell receives the influence of the application time period depending upon the erase operation to be performed to the memory cell.
In order to solve the above gate disturb phenomenon, a potential (to be referred to as a source bias voltage hereinafter) is supplied to the common source node CS1 of the memory cell array block 11 which does not contain the selected memory cell C000. The state of the memory cell at this time will be described with reference to FIGS. 3B and 3C.
FIG. 3B is a diagram illustrating the state in which the source bias voltage is applied to the non-selected memory cell. Referring to FIG. 3B, in order to solve the gate disturb phenomenon, the source bias voltage of about 2.75 V is applied to the source terminal. The drain terminal and the control gate are applied with the voltage of about 2.75 V and the voltage of about 12 V, respectively. As a result, the electric field which directs from the control gate (CG) toward the source terminal (S), the drain (D), and the channel section is weakened so that the tunneling phenomenon of electrons is restrained in the memory cells C100 to C1m0.
FIG. 3C is a diagram illustrating the source bias effect of the memory cells such as the memory cells C10n to C1mn which do not receive gate disturb. Referring to FIG. 3C, the control gate (CG) in this case is grounded. The drain is opened and the voltage of about 2.75 V is applied to the source terminal. The electric field directs from the source terminal (S) toward control gate (CG). At this time, if a lot of electrons are accumulated in the floating gate (FG), the strong electric field is generated between the source terminal (S) and the floating gate (FG), so that electrons performs tunneling toward the source terminal (This phenomenon is referred to as soft-erase hereinafter). This soft-erase causes movement of electrons in the opposite direction to the gate disturb, and also it causes the problem when a data is held.
Next, FIG. 4 is a graph illustrating a relation of threshold voltage change quantity of a memory cell and source bias voltage. Referring to FIG. 4, a curve A indicates the threshold voltage change quantity of the memory cell which receives gate disturb. The threshold voltage change quantity of the memory cell becomes small and at last becomes 0, as the source bias voltage becomes high. Also, a curve C indicates the threshold voltage change quantity of the memory cell which receives the soft-erase. The threshold voltage change quantity of the memory cell becomes large as the source bias voltage becomes high. As seen from FIG. 4, when a source bias voltage is determined in the flash memory, it is necessary that the source bias voltage is set to solve the gate disturb and the soft-erase. For this purpose, in the conventional example, a memory cell threshold voltage permission value VA is set (alternate long and short dash line in the figure). The source bias voltage PG and PS are determined such that the threshold voltage does not exceed this permission value VA because of prevention of the gate disturb and soft-erase. Then, the source bias voltage is set to a voltage P1 as a middle value between the voltages Pg and PS.
Referring to FIG. 2, in the circuit section of the source bias voltage generating circuit 200 for the memory cell array block 11, the gate voltage of the MOS transistor NT0 is set by adjusting the resistors R1 to Rn which are connected in series between the power supply Vpp and the ground. The source bias voltage P1 which has been determined as above-mentioned is outputted as the output potential. This output voltage is supplied to the source voltage supplying circuit 21 as the source power supply VS. When the erase operation is performed to the memory cell array block 10, an erasure voltage Vpp is applied to the memory cell array block 10 via the MOS transistor P01 which is controlled in response to the signal EB0, and the source bias voltage vs is applied to the memory cell array block 11 via the MOS transistor N11 which is controlled in response to the signal SB1.
As described above, when the erase and write operations are repeatedly performed to the memory cells of the flash memory, the characteristic of the memory cell changes in accordance with the number of times of the repetition of the erase and write operations, more particularly, the write time period and the erasure time period. With this, the memory cell receives the above-mentioned gate disturb and soft-erase and changes the characteristic. Especially, the characteristic change of the memory cell which receives the soft-erase is conspicuous. This seems to be the phenomenon caused when electrons are trapped in the tunnel gate oxide film of the memory cell. However, the detail is not clear.
Referring to FIG. 4 once again, the characteristic change of the memory cell which receives the soft-erase will be described. As mentioned above, the curve C indicates the threshold voltage change quantity to the source bias voltage in the memory cell which receives the soft-erase. Especially, the curve C indicates the threshold voltage change of the memory cell receiving the soft-erase when there is the small number of times of the repetition of the write and erase operations. When the number of times of the repetition the write and erase operations increases, the soft-erase characteristic of the memory cell moves to the right direction, as shown by a curve B. Also, the source bias voltage PS having the permission level VA moves to the right direction when the threshold voltage changes by the soft-erase. In the conventional method, however, the source bias voltage PS is set based on the value when there is the small number of times of the repetition of the write and erase operations. Therefore, the set source bias voltage PS has a difference from an optimal source bias voltage of the memory cell which is subjected to the repetitive write and erase operations many times. Therefore, the source bias voltage has a greater margin to the soft-erase. On the other hand, the source bias voltage is relatively more severely to the gate disturb than the soft-erase set.
In this manner, in the above-mentioned conventional non-volatile semiconductor memory device, the source bias voltage is determined such that a threshold voltage change quantity due to the gate disturb and the soft-erase does not exceed the permission level. Also, the source bias voltage is set to the middle value. However, in this case, the source bias voltage is set based on the value when there is a small repetition number of times of the write/erase operation. Therefore, the margin to the soft-erase increases more with respect to an optimal source bias voltage of the memory cell receiving the many repetition number of times of the write/erase operation. There is a problem more severely to the gate disturb than the soft-erase set.